Reference is now made to FIGS. 1-9 showing process steps for fabricating an integrated circuit transistor device such as a MOSFET transistor. It will be understood that the illustrations provided do not necessarily show the features drawn to scale.
The process starts with a substrate 10 as shown in FIG. 1. The substrate 10 comprises, for example, a silicon on insulator (SOI) substrate including a semiconductor substrate layer 12, an insulating (buried oxide) layer 14 and a semiconductor layer 16. The SOI substrate may, for example, be of a conventional SOI-type or comprise an extremely thin silicon on insulator (ETSOI) type or an ultra-thin body and buried oxide (UTBB) silicon on insulator type as known to those skilled in the art. The semiconductor layer 16 may be formed of any suitable semiconductor material, including silicon or silicon-germanium, and may be doped as appropriate for the given transistor application. In an embodiment, the SOI substrate 10 may be of the fully-depleted type (known in the art by the acronym FD-SOI). In an example implementation, the semiconductor substrate layer 12 may have a thickness of 500-800 nm, the insulating (buried oxide) layer 14 may have a thickness of 20-100 nm and the semiconductor layer 16 may have a thickness of 6-20 nm. Techniques for fabricating SOI substrates are well known to those skilled in the art and SOI wafers for use in semiconductor fabrication processes are available from a number of known commercial sources.
Next, an active region 20 of the substrate 10 is delimited by the formation of shallow trench isolation (STI) structures 22. The result is shown in FIG. 2. Any suitable process known to those skilled in the art for the formation of STI structures may be used. The active region is reserved for the formation of one or more transistor devices (for example, of the MOSFET-type). The techniques described herein are applicable to transistors of both the n-type and p-type of conductivity.
FIG. 3 shows the deposition of a high-k metal gate stack layer 26 on the top surface of the semiconductor layer 16. The stack layer 26 may, for example, comprise a pedestal high-k dielectric layer and a metal gate electrode layer. For example, the high-k dielectric can be hafnium oxide or hafnium silicate, nitrided or not, deposited in a layer using Metal Organic Chemical Vapor Deposition (MOCVD) or Atomic Layer Deposition (ALD), with a thickness from 2 to 5 nm. The metal gate electrode, such as titanium nitride, may be deposited in a layer using Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD) with a thickness of 2-20 nm.
A polysilicon layer 30 is then deposited on top of the high-k metal gate stack layer 26. The result is shown in FIG. 4. The polysilicon layer 30 may be deposited using a low pressure chemical vapor deposition (LPCVD) process to a thickness of, for example, 20-60 nm. The polysilicon layer 30 may be doped as necessary for the transistor application.
A hard mask layer 34 is then deposited on top of the polysilicon layer 30. The hard mask layer 34 may, for example, comprise an oxide layer (made of silicon, oxide, hydrogen and nitrogen atoms) and deposited using a plasma enhanced chemical vapor deposition (PECVD) process. Alternatively, the hard mask layer 34 may comprise a multi-layer structure such as with an oxide-nitride-oxide stack of layers deposited using a PECVD process. The hard mask layer 34 may, for example, have a thickness of 20-70 nm. The result is shown in FIG. 5.
Using conventional photolithographic processing techniques known to those skilled in the art, the hard mask layer 34 is patterned to define masking portions 38 as shown in FIG. 6 at locations where a gate of the transistor is desired.
An etching process (such as, for example, a reactive ion etch (RIE)) is then used to remove the portions of the layers 26 and 30 which are not covered by the masking portions 38 (thus exposing the top surface of the semiconductor layer 16). The result of this etch is shown in FIG. 7 to form a gate stack 40 including a high-k/metal gate layer 42 (from patterned layer 26), a polysilicon gate 44 (from patterned layer 30) and a cap (formed by the masking portion 38).
A conformal layer 50 of an insulating spacer material is then deposited over the substrate. The layer 50 may, for example, comprise a silicon nitride (Si3N4) material deposited using a low pressure chemical vapor deposition (LPCVD) process or atomic layer deposition (ALD) process with a thickness of 3-13 nm. The result is shown in FIG. 8.
An etching process (such as, for example, a reactive ion etch) is then performed which preferentially removes portions of the conformal layer 50 which lie on horizontal surfaces of the wafer. The result of this etch is shown in FIG. 9 to form sidewall spacers 52 on the side walls of the gate stack 40.
An epitaxial growth process as known to those skilled in the art is then performed to grow an epitaxial semiconductor layer 60 on the top surface of the semiconductor layer 16. The result is also shown in FIG. 9. The layer 60 may, for example, comprise silicon, silicon carbide or silicon germanium epitaxially grown to a thickness of 10-40 nm. The layer 60 may, if desired, be in situ doped in accordance with the transistor application. The portions of the layer 60 on each side of the gate stack 40 adjacent to the sidewall spacers 52 are provided to form raised source-drain regions 62 for the transistor. The channel of the transistor is provided by the portion of the semiconductor layer 16 located underneath the gate stack 40.
It is understood by those skilled in the art that the etching process for preferential removal of the horizontal portions of the layer 50 may be followed by a pre-epitaxial desoxidation (referred to as a hydrofluoric (HF) acid last processing step) which does not remove any more of the layer 50 but effectuates a cleaning of the top surface of the semiconductor layer 16 in preparation for subsequent epitaxial growth.
It is noted that due to the presence of the raised source-drain regions 62 with the sidewall spacers 52, the parasitic capacitance between the source or drain region and the polysilcon gate 44 electrode can be unacceptably high because of the higher k silicon nitride dielectric materials typically used for the sidewall spacers 52, thus leading to a loss in dynamic performance of the transistor device.
There would be an advantage if the sidewall spacers 52 could be made of a lower k dielectric material. The prior art notes the possible use of relatively-lower k dielectric materials in sidewall spacer formation. However, such materials often require a relatively high process temperature (for example, >500° C.) which is disadvantageous with respect to other processing steps. Still further, such relatively-lower k dielectric materials (for example, silicon oxycarbonitride (SiOCN)) can be damaged by the etch and desoxidation process steps. Indeed, such materials can be converted from a lower k material (such as SiOCN) which addresses the concerns with parasitic capacitance to a higher k material (such as silicon dioxide) with a corresponding loss of the desired lower k dielectric characteristic.
There is accordingly a need in the art to address the foregoing and other concerns with the fabricating of transistor devices with low-k dielectric sidewall spacers.